与前一题相似，只不过多了一个输出

前一题是参考别人的答案写的，自己写了输出逻辑，自己前一题的想法是没有中间八个比特的依次输入，让语句延迟8个时间单位后在进行状态判断，结果错误。

判断结果done输出1时应该是当前状态已经是接收8bit且in=1（此数据不会被丢弃），如果仅仅是下一个状态为stop-ok ，则会导致错误，因为从stop-notok状态也有可能转移到stop-ok状态。

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    parameter idel=0,start=11,b1=1,b2=2,b3=3,b4=4,b5=5,b6=6,b7=7,b8=8,stop_ok=9,stop_notok=10;
    reg [3:0] state,next_state;

    // Use FSM from Fsm_serial
    always @(*)
        begin
            case(state)
                idel:
                    next_state<=in?idel:start;
                start:
                    next_state<=b1;
                b1:
                    next_state<=b2;
                b2:
                    next_state<=b3;
                b3:
                    next_state<=b4;
                b4:
                    next_state<=b5;
                b5:
                    next_state<=b6;
                b6:
                    next_state<=b7;
                b7:
                    next_state<=b8;
                b8:
                    next_state<=in?stop_ok:stop_notok;
                stop_ok:
                    next_state<=in?idel:start;
                stop_notok:
                    next_state<=in?stop_ok:stop_notok;
                default:
                    next_state<=idel;
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset)
                state<=idel;
            else
                state<=next_state;
        end
    

    // New: Datapath to latch input bits.
    always@(posedge clk)
        begin
            done<=(state==b8&&in==1);
        end
    
    always@(posedge clk)
        begin
            if(next_state==b1)
                out_byte[0]<=in;
            if(next_state==b2)
                out_byte[1]<=in;
            if(next_state==b3)
                out_byte[2]<=in;
            if(next_state==b4)
                out_byte[3]<=in;
            if(next_state==b5)
                out_byte[4]<=in;
            if(next_state==b6)
                out_byte[5]<=in;
            if(next_state==b7)
                out_byte[6]<=in;
            if(next_state==b8)
                out_byte[7]<=in;
        end

endmodule