module top_module (
input [3:1] y,
input w,
output Y2);
parameter a=3'b000,b=3'b001,c=3'b010,d=3'b011,e=3'b100,f=3'b101;
reg [3:1] next_state;
always@(*)
begin
case(y)
a:
next_state<=w?a:b;
b:
next_state<=w?d:c;
c:
next_state<=w?d:e;
d:
next_state<=w?a:f;
e:
next_state<=w?d:e;
f:
next_state<=w?d:c;
endcase
end
assign Y2=next_state[2];
endmodule